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| LTC1264-7 Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter FEATURES s s s s s DESCRIPTIO s s Steeper Roll-Off Than Bessel Filters High Speed: fC 200kHz Phase Equalized Filter in a 14-Pin Package Phase and Group Delay Response Fully Tested Transient Response Exhibits 5% Overshoot and No Ringing 65dB THD or Better Throughout a 100kHz Passband No External Components Needed The LTC1264-7 is a clock-tunable monolithic 8th order lowpass filter with linear passband phase and flat group delay. The amplitude response approximates a maximally flat passband and exhibits steeper roll-off than an equivalent 8th order Bessel filter. For instance, at twice the cutoff frequency the filter attains 28dB attenuation (vs 12dB for Bessel), while at three times the cutoff frequency the filter attains 55dB attenuation (vs 30dB for Bessel). The cutoff frequency of the LTC1264-7 is tuned via an external TTL or CMOS clock. The clock-to-cutoff frequency ratio of the LTC1264-7 can be set to 25:1 (pin 10 to V +) or 50:1 (pin 10 to V -). When the filter operates at clock-to-cutoff frequency ratio of 25:1, the input is double-sampled to lower the risk of aliasing. The LTC1264-7 is optimized for speed. Depending on the operating conditions, cutoff frequencies between 200kHz and 250kHz can be obtained. (Please refer to the Passband vs Clock Frequency graphs.) The LTC1264-7 is pin-compatible with the LTC1064-X series. APPLICATI s s s S Data Communication Filters Time Delay Networks Phase Matched Filters TYPICAL APPLICATI 1 VIN 2 3 8V 4 5 6 7 LTC1264-7 4-Level PAM Eye Diagram 14 13 12 11 10 9 8 1264-7 TA01 200kHz Linear Phase Lowpass Filter -8V fCLK = 5MHz 8V VOUT 1V/DIV NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A 0.1F CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT PIN AND THE fCLK LINE. fCLK = 5MHz fC = 200kHz U 500ns/DIV 1264-7 TA02 UO UO 1 LTC1264-7 ABSOLUTE AXI U RATI GS (Note 1) Operating Temperature Range LTC1264-7C ...................................... - 40C to 85C LTC1264-7M ................................... - 55C to 125C Lead Temperature (Soldering, 10 sec)................. 300C Total Supply Voltage (V + to V -) .......................... 16.5V Power Dissipation............................................. 400mW Burn-In Voltage ................................................... 16.5V Voltage at Any Input ..... (V - - 0.3V) VIN (V + + 0.3V) Storage Temperature Range ............... - 65C to 150C PACKAGE/ORDER I FOR ATIO TOP VIEW NC VIN GND V+ NC LP (A) RIN (A) 1 2 3 4 5 6 7 14 OUT (C) 13 NC 12 V - 11 fCLK 10 25/50 9 8 VOUT NC ORDER PART NUMBER LTC1264-7CN LTC1264-7CJ LTC1264-7MJ J PACKAGE 14-LEAD CERAMIC DIP N PACKAGE 14-LEAD PLASTIC DIP TJMAX = 150C, JA = 65C/W (J ) TJMAX = 110C, JA = 65C/W (N ) ELECTRICAL CHARACTERISTICS PARAMETER Passband Gain Gain at 0.50 fCUTOFF (Note 3) Gain at 0.75 fCUTOFF Gain at fCUTOFF Gain at 2.0 fCUTOFF Gain with fCLK = 20kHz Gain with fCLK = 400kHz, VS = 2.375V Gain with fCLK = 4MHz VS = 7.5V, RL = 10k, TA = 25C, fCUTOFF = 100kHz or 50kHz, fCLK = 2.5MHz, TTL or CMOS level (maximum clock rise or fall time 1s) and all gain measurements are referenced to passband gain, unless otherwise specified. CONDITIONS 0.1Hz f 0.25 fCUTOFF fTEST = 25kHz, (f CLK / fC) = 25:1 fTEST = 50kHz, (f CLK / fC) = 25:1 fTEST = 25kHz, (f CLK / fC) = 50:1 fTEST = 75kHz, (f CLK / fC) = 25:1 fTEST = 100kHz, (f CLK / fC) = 25:1 fTEST = 50kHz, (f CLK / fC) = 50:1 fTEST = 200kHz, (f CLK / fC) = 25:1 fTEST = 100kHz, (f CLK / fC) = 50:1 fTEST = 200Hz, (f CLK / fC) = 50:1 fTEST = 8kHz, (fCLK / fC) = 25:1 fTEST = 16kHz, (f CLK / fC) = 25:1 fTEST = 160kHz, VIN = 1VRMS (fCLK / fC) = 25:1, TA = 0C to 70C (fCLK / fC) = 25:1 (f CLK / fC) = 25:1, f fCUTOFF (f CLK / fC) = 50:1, f fCUTOFF (f CLK / fC) = 25:1, f fCUTOFF (f CLK / fC) = 50:1, f fCUTOFF (f CLK / fC) = 25:1, f fCUTOFF (f CLK / fC) = 50:1, f fCUTOFF (f CLK / fC) = 25:1, f fCUTOFF (f CLK / fC) = 50:1, f fCUTOFF MIN q q q q q q q q Phase Factor (F ) Phase = 180 - F (f/fC) (Note 1) Phase Nonlinearity (Note 1) 2 U U W WW U W TOP VIEW NC 1 VIN 2 GND 3 V+ 4 16 OUT (C) 15 NC 14 V - 13 NC 12 fCLK 11 25/50 10 NC 9 S PACKAGE 16-LEAD PLASTIC SOL VOUT ORDER PART NUMBER LTC1264-7CS NC 5 NC 6 LP (A) 7 RIN (A) 8 TJMAX = 110C, JA = 85C/W TYP - 0.10 - 0.15 -1.0 - 3.0 - 3.0 - 28 - 30 - 0.3 0.15 - 2.70 0.00 1.0 MAX 0.50 0.20 0.30 0.1 -1.9 - 2.3 - 20 - 27 0.1 0.5 - 1.4 UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB Deg Deg Deg Deg % % % % - 0.50 - 0.50 - 0.65 - 1.5 - 3.7 - 4.5 - 34 - 34 - 0.7 - 0.2 - 3.5 q 3.0 407 2 388 2 q q 392 374 1.0 1.0 423 414 q q 2.0 2.0 LTC1264-7 ELECTRICAL CHARACTERISTICS VS = 7.5V, RL = 10k, TA = 25C, fCUTOFF = 100kHz or 50kHz, fCLK = 2.5MHz, TTL or CMOS level (maximum clock rise or fall time 1s) and all gain measurements are referenced to passband gain, unless otherwise specified. PARAMETER Group Delay (td) td = (F/ 360)(1/fC); (Note 2, 3) Group Delay Ripple (Note 2) CONDITIONS (f CLK / fC) = 25:1, f fCUTOFF (f CLK / fC) = 50:1, f fCUTOFF (f CLK / fC) = 25:1, f fCUTOFF (f CLK / fC) = 50:1, f fCUTOFF (f CLK / fC) = 25:1, f fCUTOFF (f CLK / fC) = 50:1, f fCUTOFF (f CLK / fC) = 25:1, f fCUTOFF (f CLK / fC) = 50:1, f fCUTOFF (f CLK / fC) = 25:1 (f CLK / fC) = 50:1 VS = Single 5V (GND = 2V) VS = 5V VS = 7.5V 25:1, 7.5V, f = fCLK VS = Single 5V VS = 5V VS = 7.5V VS = 2.375V VS = 5V VS = 7.5V 25:1, VS = 5V 50:1, VS = 5V 25:1, VS = 5V 50:1, VS = 5V VS = 2.375V VS = 5V q MIN TYP 11.3 21.6 MAX q q 10.9 20.8 1.0 1.0 11.7 22.9 q q 2.0 2.0 Input Frequency Range (Table 9, 10) Maximum fCLK Clock Feedthrough Wideband Noise (1Hz f < fCLK) Input Impedance Output DC Voltage Swing (Note 4) Output DC Offset (fCLK = 1MHz) Output DC Offset TempCo Power Supply Current (fCLK = 1MHz) 30 q q 2.0 3.0 220 220 q VS = 7.5V q Power Supply Range The q denotes specifications which apply over the full operating temperature range. Note 1: Input frequencies, f, are linearly phase shifted through the filter as long as f fC; fC = cutoff frequency. Figure 1 curve (A) shows the typical phase response of an LTC1264-7 operating at fCLK = 2.5MHz, fC = 100kHz. An endpoint straight line, curve (B), depicts the ideal linear phase response of the filter. It is described by: phase shift = 180 - F (f/fC); f fC. F is arbitrarily called the "phase factor" expressed in degrees. The phase factor together with the specified deviation from the ideal straight line allows the calculation of the phase at a given frequency. Note, the maximum phase nonlinearity, Figure 1, occurs at the vicinity of f = 0.25 fC and = 0.75 fC. Example: The phase shift at 70kHz of the LTC1264-7 shown in Figure 1 is: phase shift = 180 - 407 (70kHz/100kHz) nonlinearity =- 104.9 1% or -104.9 1.05. Note 2: Group delay and group delay deviation are calculated from the measured phase factor and phase deviation specifications. Note 3: The filter cutoff frequency is abbreviated as fCUTOFF or fC. Note 4: The AC swing is typically 9VP-P, 5.6VP-P, 1.8VP-P with 7.5V, 5V, 2.5V supply respectively. For more information refer to the THD + Noise vs Input graphs. 2.375 22 22 23 26 28 32 8 UNITS s s s s % % % % kHz kHz MHz MHz MHz VRMS VRMS VRMS VRMS k V V V mV mV V/C V/C mA mA mA mA mA mA V 180 90 0 -90 A B fCLK = 2.5MHz (fCLK /fC) = 25:1 PHASE (DEG) -180 -270 -360 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) LTC1264-7 F01 Figure 1. Phase Response in the Passband (Note 1) 3 LTC1264-7 TYPICAL PERFOR A CE CHARACTERISTICS Gain vs Frequency 10 0 -10 -20 PHASE FACTOR GAIN (dB) VS = 7.5V fCLK = 1MHz TA = 25C -30 -40 -50 -60 -70 -80 -90 -100 1 10 100 FREQUENCY (kHz) 1000 1264-7 G01 PHASE FACTOR 50:1 25:1 Phase Factor vs fCLK (Min and Max Representative Units) 450 445 440 435 PHASE FACTOR 430 425 420 415 410 405 400 395 0 1 3 2 fCLK (MHz) 4 5 1264-7 G04 VS = 7.5V (fCLK /fC) = 25:1 TA = 25C PHASE FACTOR Passband Gain and Phase 3 2 1 0 GAIN (dB) -2 -3 -4 -5 -6 VS = 7.5V fCLK = 2.5MHz fC = 100kHz (fCLK /fC) = 25:1 PHASE -45 -90 -135 -180 -225 GAIN (dB) -1 -270 -7 10 20 30 40 50 60 70 80 90 100 110 FREQUENCY (kHz) 1264-7 G06 4 UW Phase Factor vs fCLK (Typical Unit) 460 450 440 430 420 410 400 390 0 1 3 2 fCLK (MHz) 4 5 1264-7 G02 Phase Factor vs fCLK (Typical Unit) 450 440 70C 430 25C 420 410 0C 400 390 380 370 0 1 3 2 fCLK (MHz) 4 5 1264-7 G03 VS = 7.5V (fCLK /fC) = 25:1 VS = 7.5V (fCLK /fC) = 50:1 70C 25C 0C Phase Factor vs fCLK (Min and Max Representative Units) 425 420 415 410 405 400 395 VS = 5V (fCLK /fC) = 25:1 TA = 25C 0 0.5 1.0 1.5 2.0 fCLK (MHz) 2.5 3.0 1264-7 G05 Passband Gain and Phase 180 135 90 45 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 5 VS = 7.5V fCLK = 2.5MHz fC = 50kHz (fCLK /fC) = 50:1 PHASE GAIN PHASE (DEG) 180 135 90 45 PHASE (DEG) GAIN 0 0 -45 -90 -135 -180 -225 -270 10 15 20 25 30 35 40 45 50 55 FREQUENCY (kHz) 1264-7 G07 LTC1264-7 TYPICAL PERFOR A CE CHARACTERISTICS Passband Gain vs fCLK 5 4 3 2 VS = 7.5V (fCLK /fC) = 25:1 TA = 25C A. fCLK = 1MHz B. fCLK = 2MHz C. fCLK = 3MHz D. fCLK = 4MHz E. fCLK = 5MHz 5 4 3 2 VS = 7.5V (fCLK /fC) = 50:1 TA = 25C A. fCLK = 1MHz B. fCLK = 2MHz C. fCLK = 3MHz D. fCLK = 4MHz E. fCLK = 5MHz GAIN (dB) GAIN (dB) 0 -1 -2 -3 -4 -5 10 100 FREQUENCY (kHz) 1000 1264-7 G08 0 -1 -2 A B CDE GAIN (dB) 1 A B C DE Passband Gain vs fCLK at 85C 5 4 3 2 VS = 5V (fCLK /fC) = 25:1 A. fCLK = 1MHz B. fCLK = 2MHz C. fCLK = 3MHz 10 0 -10 -20 GAIN (dB) GAIN (dB) 0 -1 -2 A -3 -4 -5 10 100 FREQUENCY (kHz) 1000 1264-7 G11 -40 -50 -60 VS = 7.5V fCLK = 5MHz (fCLK /fC) = 25:1 TA = 25C 10 100 FREQUENCY (kHz) 1000 1264-7 G12 GAIN (dB) 1 B C Gain vs fCLK 10 0 -10 -20 GAIN (dB) A B GAIN (dB) GAIN (dB) -30 -40 -50 -60 -70 -80 -90 10 FREQUENCY (kHz) 1264-7 G14 A. fCLK = 0.5MHz B. fCLK = 1MHz C. fCLK = 2MHz VS = SINGLE 5V (fCLK /fC) = 25:1 AGND = 2V TA = 25C 100 200 UW C Passband Gain vs fCLK 5 4 3 2 1 0 -1 -2 -3 -4 -5 10 100 FREQUENCY (kHz) 1000 1264-7 G09 Passband Gain vs fCLK at 85C VS = 7.5V (fCLK /fC) = 25:1 A. fCLK = 4MHz B. fCLK = 5MHz 1 A B -3 -4 -5 10 100 FREQUENCY (kHz) 1000 1264-7 G10 Gain vs Frequency 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 Gain vs Frequency -30 -70 -80 -90 VS = 5V fCLK = 3MHz (fCLK /fC) = 25:1 TA = 25C 10 100 FREQUENCY (kHz) 1000 1264-7 G13 Passband Gain vs fCLK 5 4 3 2 1 0 -1 -2 -3 -4 -5 10 FREQUENCY (kHz) 1264-7 G15 Maximum Passband vs Temperature 2 1 A 0 -1 -2 -3 A. TA = 70C B. TA = -40C VS = SINGLE 5V fCLK = 2MHz (fCLK /fC) = 25:1 AGND = 2V 1 10 FREQUENCY (kHz) 100 1264-7 G16 VS = SINGLE 5V (fCLK /fC) = 25:1 AGND = 2V TA = 25C A. fCLK = 0.5MHz B. fCLK = 1.0MHz C. fCLK = 1.5MHz D. fCLK = 2.0MHz B A B C D -4 -5 100 200 5 LTC1264-7 TYPICAL PERFOR A CE CHARACTERISTICS Gain vs fCLK 10 0 -10 -20 A B A. fCLK = 0.5MHz B. fCLK = 1MHz C. fCLK = 2MHz C GAIN (dB) GAIN (dB) GAIN (dB) -30 -40 -50 -60 -70 -80 -90 10 VS = SINGLE 5V (fCLK /fC) = 50:1 AGND = 2V TA = 25C 100 FREQUENCY (kHz) 1264-7 G17 Delay vs fCLK 30 A 25 20 VS = 7.5V (fCLK /fC) = 25:1 TA = 25C A. fCLK = 1MHz B. fCLK = 2MHz C. fCLK = 3MHz D. fCLK = 4MHz 60 50 40 DELAY (s) DELAY (s) 15 10 5 0 B C D 30 20 10 0 B C D THD (dB) 20 40 60 80 100 120 140 160 180 200 220 INPUT FREQUENCY (kHz) 1264-7 G20 THD vs Frequency -40 -45 -50 -55 VS = 7.5V VIN = 1VRMS fCLK = 2.5MHz (fCLK /fC) = 25:1 (5 REPRESENTATIVE UNITS) THD (dB) THD (dB) -60 -65 -70 -75 -80 -85 -90 1 THD + NOISE (dB) 10 FREQUENCY (kHz) 6 UW 1264-7 G23 Passband Gain vs fCLK 5 4 3 2 1 0 -1 -2 -3 -4 200 1.0 Maximum Passband vs Temperature 0.5 0 - 0.5 -1.0 -1.5 -2.0 -2.5 -3.0 A. TA = 70C B. TA = -40C A B VS = SINGLE 5V (fCLK /fC) = 50:1 AGND = 2V TA = 25C A. fCLK = 0.5MHz B. fCLK = 1.0MHz C. fCLK = 1.5MHz D. fCLK = 2.0MHz A B C D -3.5 VS = SINGLE 5V fCLK = 2MHz (fCLK /fC) = 50:1 AGND = 2V 1 10 FREQUENCY (kHz) 50 1264-7 G19 -5 5 10 FREQUENCY (kHz) 1264-7 G18 100 -4.0 Delay vs fCLK -40 A VS = 7.5V (fCLK /fC) = 50:1 TA = 25C -45 -50 -55 A. fCLK = 1MHz B. fCLK = 2MHz C. fCLK = 3MHz D. fCLK = 4MHz -60 -65 -70 -75 -80 -85 -90 10 20 30 40 50 60 70 80 90 100 110 INPUT FREQUENCY (kHz) 1264-7 G21 THD vs Frequency VS = 5V VIN = 1VRMS fCLK = 1MHz (fCLK /fC) = 25:1 (5 REPRESENTATIVE UNITS) 1 10 FREQUENCY (kHz) 50 1264-7 G22 THD vs Frequency -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 100 -40 THD + Noise vs Input -45 -50 -55 -60 -65 -70 -75 -80 -85 fIN = 1kHz fCLK = 1MHz (fCLK /fC) = 25:1 A. VS = 5V B. VS = 7.5V A B VS = SINGLE 5V VIN = 0.5VRMS fCLK = 500kHz (fCLK /fC) = 25:1 AGND = 2V (5 REPRESENTATIVE UNITS) 1 FREQUENCY (kHz) 10 20 1264-7 G24 -90 0.1 1 INPUT AMPLITUDE (VRMS) 5 1264-7 G25 LTC1264-7 TYPICAL PERFOR A CE CHARACTERISTICS THD + Noise vs Input -40 -45 -50 A. PIN 3 AT 2.5V B. PIN 3 AT 2V A B PHASE DIFFERENCE (DEG) 4 POWER SUPPLY CURRENT (mA) THD + NOISE (dB) -55 -60 -65 -70 -75 -80 -85 VS = SINGLE 5V fCLK = 500kHz fIN = 1kHz 0.1 INPUT AMPLITUDE (VRMS) 1 1264-7 G26 -90 50m Table 1. Passband Gain and Phase VS = 7.5V, (fCLK / fC) = 25:1, TA = 25C FREQUENCY (kHz) fCLK = 1MHz (Typical Unit) 0.000 10.000 20.000 30.000 40.000 fCLK = 2MHz (Typical Unit) 0.000 20.000 40.000 60.000 80.000 fCLK = 3MHz (Typical Unit) 0.000 30.000 60.000 90.000 120.000 fCLK = 4MHz (Typical Unit) 0.000 40.000 80.000 120.000 160.000 fCLK = 5MHz (Typical Unit) 0.000 50.000 100.000 150.000 200.000 GAIN (dB) 0.064 0.064 0.058 - 0.639 - 2.741 - 0.006 - 0.006 - 0.164 - 0.958 - 3.003 - 0.067 - 0.067 - 0.287 - 0.944 - 2.545 - 0.031 - 0.031 - 0.078 - 0.332 - 1.275 0.073 0.073 0.365 0.686 0.521 PHASE (DEG) 180.00 81.14 -19.18 -120.63 - 221.78 180.00 79.42 - 22.13 -124.09 - 225.01 180.00 77.49 - 25.54 - 128.51 - 230.19 180.00 75.23 - 30.06 - 135.27 - 239.76 180.00 71.77 - 37.11 - 146.19 - 255.85 UW Phase Matching vs Frequency 5 PHASE DIFFERENCE BETWEEN ANY TWO UNITS (SAMPLE OF 50 REPRESENTATIVE UNITS) VS 5V fCLK 2.5MHz (fCLK /fC) = 25:1 OR 50:1 TA = 0C TO 70C 48 44 40 36 32 28 24 20 16 12 8 4 0 Power Supply Current vs Power Supply Voltage fCLK = 1MHz 3 2 -55C 25C 125C 1 0 0 0.2 0.6 0.8 0.4 FREQUENCY (fCUTOFF/FREQUENCY) 1.0 02 4 6 8 10 12 14 16 18 20 22 24 TOTAL POWER SUPPLY VOLTAGE (V) 1264-7 G28 1264-7 G27 Table 2. Passband Gain and Phase VS = 7.5V, (fCLK / fC) = 50:1, TA = 25C FREQUENCY (kHz) fCLK = 1MHz (Typical Unit) 0.000 5.000 10.000 15.000 20.000 fCLK = 2MHz (Typical Unit) 0.000 10.000 20.000 30.000 40.000 fCLK = 3MHz (Typical Unit) 0.000 15.000 30.000 45.000 60.000 fCLK = 4MHz (Typical Unit) 0.000 20.000 40.000 60.000 80.000 fCLK = 5MHz (Typical Unit) 0.000 25.000 50.000 75.000 100.000 GAIN (dB) - 0.048 - 0.048 - 0.351 - 1.253 - 3.348 - 0.008 - 0.008 - 0.237 - 1.105 - 3.238 0.044 0.044 - 0.065 - 0.863 - 3.022 0.071 0.071 0.039 - 0.664 - 2.755 0.089 0.089 0.141 - 1.437 - 2.421 PHASE (DEG) 180.00 84.51 - 10.87 - 105.53 - 199.61 180.00 83.39 - 13.09 - 108.91 - 204.09 180.00 81.04 - 18.64 - 118.48 - 217.67 180.00 78.04 - 25.06 - 128.54 - 231.42 180.00 74.36 - 32.41 - 139.33 - 246.01 7 LTC1264-7 TYPICAL PERFOR A CE CHARACTERISTICS Table 3. Passband Gain and Phase VS = 5V, (fCLK / fC) = 25:1, TA = 25C FREQUENCY (kHz) fCLK = 1MHz (Typical Unit) 0.000 10.000 20.000 30.000 40.000 fCLK = 2MHz (Typical Unit) 0.000 20.000 40.000 60.000 80.000 fCLK = 3MHz (Typical Unit) 0.000 30.000 60.000 90.000 120.000 GAIN (dB) 0.081 0.081 0.071 - 0.631 - 2.732 - 0.016 - 0.016 - 0.211 - 0.968 - 2.864 - 0.006 - 0.006 - 0.044 - 0.369 - 1.507 PHASE (DEG) 180.00 80.94 - 19.54 - 121.10 - 222.28 180.00 78.78 - 23.21 - 125.42 - 226.47 180.00 76.07 - 28.54 - 133.27 - 237.35 Table 5. Passband Gain and Phase VS = Single 5V, (fCLK /fC) = 25:1, TA = 25C FREQUENCY (kHz) fCLK = 0.5MHz (Typical Unit) 0.000 5.000 10.000 15.000 20.000 fCLK = 1MHz (Typical Unit) 0.000 10.000 20.000 30.000 40.000 fCLK = 1.5MHz (Typical Unit) 0.000 15.000 30.000 45.000 60.000 fCLK = 2MHz (Typical Unit) 0.000 20.000 40.000 60.000 80.000 GAIN (dB) 0.161 0.161 0.166 - 0.515 - 2.598 0.125 0.125 0.043 - 0.706 - 2.781 0.061 0.061 - 0.096 - 0.741 - 2.432 0.151 0.151 0.321 0.203 - 0.838 PHASE (DEG) 180.00 81.47 - 18.52 - 119.79 - 220.82 180.00 80.23 - 20.75 - 122.53 - 223.59 180.00 78.49 - 23.82 - 126.47 - 228.12 180.00 75.03 - 31.15 - 137.86 - 244.58 8 UW Table 4. Passband Gain and Phase VS = 5V, (fCLK / fC) = 50:1, TA = 25C FREQUENCY (kHz) fCLK = 1MHz (Typical Unit) 0.000 5.000 10.000 15.000 20.000 fCLK = 2MHz (Typical Unit) 0.000 10.000 20.000 30.000 40.000 fCLK = 3MHz (Typical Unit) 0.000 15.000 30.000 45.000 60.000 GAIN (dB) 0.032 0.032 - 0.249 - 1.135 - 3.225 0.101 0.101 - 0.043 - 0.864 - 3.021 0.125 0.125 0.043 - 0.753 - 2.987 PHASE (DEG) 180.00 84.60 - 10.65 - 105.20 - 199.22 180.00 82.47 - 15.45 - 113.28 - 210.54 180.00 77.88 - 25.31 - 128.74 - 231.29 Table 6. Passband Gain and Phase VS = Single 5V, (fCLK /fC) = 50:1, TA = 25C FREQUENCY (kHz) fCLK = 0.5MHz (Typical Unit) 0.000 2.500 5.000 7.500 10.000 fCLK = 1MHz (Typical Unit) 0.000 5.000 10.000 15.000 20.000 fCLK = 1.5MHz (Typical Unit) 0.000 7.500 15.000 22.500 30.000 fCLK = 2MHz (Typical Unit) 0.000 10.000 20.000 30.000 40.000 GAIN (dB) 0.075 0.075 - 0.217 - 1.108 - 3.198 0.114 0.114 - 0.122 - 0.988 - 3.111 0.174 0.174 0.066 - 0.744 - 2.949 0.232 0.232 0.219 - 0.599 - 3.031 PHASE (DEG) 180.00 84.79 - 10.40 - 105.10 - 199.26 180.00 83.96 - 11.88 - 107.02 - 201.63 180.00 81.36 - 17.84 - 117.12 - 215.79 180.00 75.98 - 29.26 - 134.63 - 239.09 LTC1264-7 PI FU CTIO S Power Supply Pins (4, 12) The V + (pin 4) and the V - (pin 12) should each be bypassed with a 0.1F capacitor to an adequate analog ground. The filter's power supplies should be isolated from other digital or high voltage analog supplies. A low noise linear supply is recommended. Using a switching power supply will lower the signal-to-noise ratio of the filter. The supply during power-up should have a slew rate less than 1V/s. When V + is applied before V - and V - is allowed to go above ground, a signal diode should clamp V - to prevent latch-up. Figures 2 and 3 show typical connections for dual and single supply operation. Clock Input Pin (11) Any TTL or CMOS clock source with a square-wave output and 50% duty cycle (10%) is an adequate clock source for the device. The power supply for the clock source should not be the filter's power supply. The analog ground for the filter should be connected to clock's ground at a single point only. Table 7 shows the clock's low and high level threshold values for a dual or single supply operation. A pulse generator can be used as a clock source provided the high level ON time is greater than 0.1s. Sine waves are not recommended for clock input frequencies less than 100kHz, since excessively slow clock rise or fall times generate internal clock jitter (maximum clock rise or fall time 1s). The clock signal should be routed from the right side of the IC package and perpendicular to it to avoid coupling to any input or output analog signal path. A 200 resistor between clock source and pin 11 will slow down the rise and fall times of the clock to further reduce charge coupling (Figures 2 and 3). Table 7. Clock Source High and Low Threshold Levels POWER SUPPLY Dual Supply = 7.5V Dual Supply = 5V Dual Supply = 2.5V Single Supply = 12V Single Supply = 5V HIGH LEVEL 2.18V 1.45V 0.73V 7.80V 1.45V LOW LEVEL 0.5V 0.5V - 2.0V 6.5V 0.5V VIN V+ 0.1F 10k Analog Ground Pins (3, 5) The filter performance depends on the quality of the analog signal ground. For either dual or single supply operation, an analog ground plane surrounding the pack- U U U age is recommended. The analog ground plane should be connected to any digital ground at a single point. For dual supply operation, pin 3 should be connected to the analog ground plane. For single supply operation pin 3 should be biased at 1/2 supply and should be bypassed to the analog ground plane with at least a 1F capacitor (Figure 3). For single 5V operation at the highest fCLK of 2MHz, pin 3 should be biased at 2V. This minimizes passband gain and phase variations. Ratio Input Pin (10) The DC level at this pin determines the ratio of the clock frequency to the cutoff frequency of the filter. Pin 10 at V + gives a 25:1 ratio and pin 10 at V - gives a 50:1 ratio. For single supply operation the ratio is 25:1 when pin 10 is at V + and 50:1 when pin 10 is at ground. When pin 10 is not tied to ground, it should be bypassed to analog ground with a 0.1F capacitor. If the DC level at pin 10 is switched mechanically or electrically at slew rates greater than 1V/s while the device is operating, a 10k resistor should be connected between pin 10 and the DC source. V- 1 VIN V+ 2 3 4 5 0.1F 6 7 LTC1264-7 14 13 12 11 10 9 8 + GND DIGITAL SUPPLY V+ 200 CLOCK SOURCE 0.1F VOUT 1264-7 F02 Figure 2. Dual Supply Operation for an fCLK/fCUTOFF = 25:1 1 2 3 4 5 6 7 LTC1264-7 14 13 12 11 10 9 8 + GND DIGITAL SUPPLY 200 CLOCK SOURCE V+ 10k + 1F VOUT 1264-7 F03 Figure 3. Single Supply Operation for an fCLK/fCUTOFF = 25:1 9 LTC1264-7 PI FU CTIO S Filter Input Pin (2) The input pin is connected internally through a 50k resistor tied to the inverting input of an op amp. Filter Output Pins (9, 6) Pin 9 is the specified output of the filter; it can typically source 3mA and sink 1mA. Driving coaxial cables or resistive loads less than 20k will degrade the total harmonic distortion of the filter. When evaluating the device's distortion an output buffer is required. A noninverting buffer, Figure 4, can be used provided that its input common-mode range is well within the filter's output swing. Pin 6 is an intermediate filter output providing an unspecified 6th order lowpass filter. Pin 6 should not be loaded. External Connection Pins (7, 14) Pins 7 and 14 should be connected together. In a printed circuit board the connection should be done under the IC package through a short trace surrounded by the analog ground plane. NC Pin (1, 5, 8, 13) 1264-7 F04 Figure 4. Buffer for Filter Output APPLICATI S I FOR ATIO Clock Feedthrough Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics that are present at the filter's output pin (9). The clock feedthrough is tested with the input pin (2) grounded and it depends on PC board layout and on the value of the power supplies. With proper layout techniques the values of the clock feedthrough are shown in Table 8. Table 8. Clock Feedthrough VS Single 5V 5V 7.5V 25:1 100VRMS 100VRMS 120VRMS 50:1 100VRMS 400VRMS 1000VRMS Note: The clock feedthrough at 25:1 is imbedded in the wideband noise of the filter. Clock waveform is a square wave. Any parasitic switching transients during the rise and fall edges of the incoming clock are not part of the clock feedthrough specifications. Switching transients have frequency contents much higher than the applied clock; their amplitude strongly depends on scope probing techniques as well as grounding and power supply bypassing. The 10 U W U + 1k - U UO U U LT1220 Pins 1, 5, 8 and 13 are not connected to any internal circuit point on the device and should be preferably tied to analog ground. clock feedthrough, if bothersome, can be greatly reduced by adding a simple R/C lowpass network at the output of the filter pin (9). This R/C will completely eliminate any switching transients. Wideband Noise The wideband noise of the filter is the total RMS value of the device's noise spectral density and it is used to determine the operating signal-to-noise ratio. Most of its frequency contents lie within the filter passband and it cannot be reduced with post filtering. For instance, the LTC1264-7 wideband noise at 5V supply is 160VRMS, 145VRMS of which have frequency contents from DC up to the filter's cutoff frequency. The total wideband noise (VRMS) is nearly independent of the value of the clock. The clock feedthrough specifications are not part of the wideband noise. Speed Limitations To avoid op amp slew rate limiting at maximum clock frequencies, the signal amplitude should be kept below a specified level as shown in Table 9. LTC1264-7 APPLICATI POWER SUPPLY 7.5V S I FOR ATIO Table 9. Maximum VIN vs VS and Clock MAXIMUM fCLK 5.0MHz 4.5MHz 4.0MHz 3.5MHz 3.0MHz 3.0MHz 2.0MHz MAXIMUM VIN 1.6VRMS (fIN 160kHz) 2.0VRMS (fIN 160kHz) 2.5VRMS (fIN 160kHz) 1.6VRMS (fIN 500kHz) 1.6VRMS (fIN 100kHz) 0.7VRMS (fIN 500kHz) 0.5VRMS (fIN 400kHz) 5V Single 5V Transient Response 2V/DIV INPUT = 10kHz 3V fCLK = 2.5MHz RATIO = 25:1 10s/DIV Figure 5. ts INPUT 90% OUTPUT 50% td 10% tr RISE TIME (tr) = 0.36 5% fCUTOFF 2 SETTLING TIME (ts) = 5% f (TO 1% of OUTPUT) CUTOFF TIME DELAY (td) = GROUP DELAY fCUTOFF (TO 50% OF OUTPUT) 1.15 1164-7 F06 Figure 6. Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U Aliasing Aliasing is an inherent phenomenon of sampled data systems and it occurs when input frequencies close to the sampling frequency are applied. For the LTC1264-7 case at 50:1, an input signal whose frequency is in the range of fCLK 10%, will be aliased back into the filter's passband. If, for instance, an LTC1264-7 operating with a 100kHz clock and 2kHz cutoff frequency receives a 95kHz 10mV input signal, a 5kHz 56VRMS alias signal will appear at its output. When the LTC1264-7 operates with a clock-tocutoff frequency of 25:1, aliasing occurs at twice the clock frequency. Table 10 shows details. Table 10. Aliasing (fCLK = 100kHz ) INPUT FREQUENCY (VIN = 1VRMS, fIN = fCLK fOUT) (kHz) 25:1, fCUTOFF = 4kHz 175 (or 225) 180 (or 220) 185 (or 215) 190 (or 210) 195 (or 205) 50:1, fCUTOFF = 2kHz 75 (or 125) 80 (or 120) 85 (or 115) 90 (or 110) 95 (or 105) 99 (or 101) OUTPUT LEVEL (Relative to Input, 0dB = 1VRMS) (dB) -76 - 69 - 62 - 43 -7 -96 - 90 - 82 - 72 - 45 0 OUTPUT FREQUENCY (Aliased Frequency fOUT = ABS [fCLK fIN]) (kHz) 25 20 15 10 5 25 20 15 10 5 1 W U UO Table 11. Transient Response of LTC Lowpass Filters DELAY TIME* (SEC) 0.50/fC 0.43/fC 0.43/fC 1.15/fC 1.20/fC 1.20/fC 0.80/fC 0.85/fC 0.90/fC 0.85/fC RISE SETTLING OVERTIME** TIME*** SHOOT (SEC) (SEC) (%) 0.34/fC 0.80/fC 0.5 0.34/fC 0.85/fC 0 0.34/fC 1.15/fC 1 0.36/fC 0.39/fC 0.39/fC 0.48/fC 0.54/fC 0.54/fC 0.54/fC 2.05/fC 2.20/fC 2.20/fC 2.40/fC 4.30/fC 4.50/fC 6.50/fC 5 5 5 11 18 20 20 LOWPASS FILTER LTC1064-3 Bessel LTC1164-5 Bessel LTC1164-6 Bessel LTC1264-7 Linear Phase LTC1164-7 Linear Phase LTC1064-7 Linear Phase LTC1164-5 Butterworth LTC1164-6 Elliptic LTC1064-4 Elliptic LTC1064-1 Elliptic * To 50% 5%, ** 10% to 90% 5%, *** To 1% 0.5% 11 LTC1264-7 PACKAGE DESCRIPTIO 0.290 - 0.320 (7.366 - 8.128) 0.008 - 0.018 (0.203 - 0.460) 0.385 0.025 (9.779 0.635) 0 - 15 0.038 - 0.068 (0.965 - 1.727) 0.014 - 0.026 (0.360 - 0.660) 0.300 - 0.325 (7.620 - 8.255) 0.015 (0.380) MIN 0.130 0.005 (3.302 0.127) 0.009 - 0.015 (0.229 - 0.381) +0.025 0.325 -0.015 +0.635 8.255 -0.381 ( ) 0.075 0.015 (1.905 0.381) 0.291 - 0.299 (7.391 - 7.595) 0.005 (0.127) RAD MIN 0.010 - 0.029 x 45 (0.254 - 0.737) 0.093 - 0.104 (2.362 - 2.642) 0.037 - 0.045 (0.940 - 1.143) 0 - 8 TYP SEE NOTE 0.009 - 0.013 (0.229 - 0.330) 0.050 (1.270) TYP 0.004 - 0.012 (0.102 - 0.305) 0.394 - 0.419 (10.007 - 10.643) SEE NOTE 0.016 - 0.050 (0.406 - 1.270) NOTE: PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977 U Dimensions in inches (millimeters) unless otherwise noted. J Package 14-Lead Ceramic DIP 0.200 (5.080) MAX 0.015 - 0.060 (0.381 - 1.524) 0.025 (0.635) RAD TYP 0.005 (0.127) MIN 0.785 (19.939) MAX 14 13 12 11 10 9 8 0.220 - 0.310 (5.588 - 7.874) 1 0.100 0.010 (2.540 0.254) 0.125 (3.175) MIN 0.098 (2.489) MAX 2 3 4 5 6 7 J14 0392 N Package 14-Lead Plastic DIP 0.065 (1.651) TYP 14 13 12 0.770 (19.558) MAX 11 10 9 8 0.045 - 0.065 (1.143 - 1.651) 0.260 0.010 (6.604 0.254) 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 1 0.125 (3.175) MIN 2 3 4 5 6 7 S Package 16-Lead Plastic SOL 16 15 0.398 - 0.413 (10.109 - 10.490) 14 13 12 11 10 9 0.014 - 0.019 (0.356 - 0.482) TYP 1 2 3 4 5 6 7 8 SOL16 0392 LT/GP 1292 10K REV 0 (c) LINEAR TECHNOLOGY CORPORATION 1992 |
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